A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1988, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" b C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al. (the related application cited above); U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; and U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
Briefly, in this high density interconnect structure, the electronic chips or components of a system are disposed in a cavity or cavities of a substrate with their upper surfaces in substantially the same plane as the upper surface of the rest of the substrate. This structure is assembled by providing a thermoplastic adhesive on the bottom of the cavity. This thermoplastic adhesive layer may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the cavity. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E. I. du Pont de Nemours Company, which is .about.0.0005-0.003 inch (.about.12.5-75 microns) thick is pretreated to promote adhesion and coated on one side with the ULTEM.RTM. polyetherimide resin or another thermoplastic and laminated across the top of the chips, other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with contact pads on the electronic components to which it is desired to make contact. A metallization layer is deposited over the Kapton.RTM. layer. This metallization extends into the via holes and makes electrical contact to contact pads disposed at the bottoms thereof. In order to provide high conductivity conductors with good adhesion, a layer of titanium or chromium is normally sputtered directly on top of the dielectric layer to provide good adhesion. A layer of copper is then sputtered on the adhesion layer. A relatively thick layer of copper is then electroplated on top of the sputtered copper layer to provide a thick, high conductivity conductor. That electroplated copper layer is coated with photoresist which is then laser exposed and developed to provide a mask for etching the copper. The copper is then etched to form a pattern of accurately aligned conductors at the end of the process. Additional dielectric and metallization layers are provided as required in order to provide the desired interconnection pattern. There is a need in this HDI system for a technique which will provide high quality, relatively thick patterned conductor layers in a more efficient manner.
Electrolytic metal deposition is a widely used industrial process having application to a wide variety of products and fields. In electronic applications where a specific metal pattern is required, electrolytic deposition may be used in either of two manners In the first, a uniform metal layer is formed by electrolytic deposition, the exposed surface of that layer is coated with a photoresist, the photoresist is then exposed in the desired pattern for the final metal structure, the photoresist is developed and the structure is etched to remove the unprotected electroplated material. In the second technique, a photoresist pattern is disposed on the conductive surface of a substrate structure, exposed and developed to expose the underlying conductive layer in the desired plating pattern. Thereafter, the structure is electroplated to produce a thick layer on the exposed portion of the underlying conductive layer. Where relatively thick conductive layers are desired, these processes both present problems with respect to the durability of the photoresist in the etching or plating bath because extended time periods in these solutions can cause deterioration of the photoresist. Sufficient deterioration of the photoresist results in plating or etching in undesired locations. Another technique for plating which can be used for a connected structure is to define the conductor to be plated with photoresist and remove the rest of the layer. This process depends on carrying the plating current through the structure being plated itself. This tends to result in non-uniform plating with the greater thickness being near the external electrical connections to the structure and progressively lesser thicknesses further from the connections. Thus, this is not a preferred method. An additional problem where fine line, thick metallic patterns are desired is the inability of both the plating-followed-by-photoresist-and-etching and the photoresist-followed-by-plating process to provide reliable definition of fine line structures. Another problem with the plating-followed-by-photoresist-and-etching process is the problem of accurately aligning the photoresist exposure mask with respect to the underlying structure on the substrate beneath a thick metal layer.
U.S. Pat. No. 4,988,412 discloses a technique which we call selective electrolytic deposition or SED. Selective electrolytic deposition overcomes many of the problems with prior electroplating techniques. In accordance with U.S. Pat. No. 4,988,412, a body to be plated is provided with an exterior surface which is comprised of two different conductive materials. One of these conductive materials forms a plating-preventing compound such as an oxide, while the other does not. The metal which does not form the plating-preventing compound is exposed at the surface in the desired plating pattern, while the remainder of the surface is the metal which forms the plating-preventing layer. The plating-preventing layer is allowed to form naturally in the case of some oxide plating-preventing compounds such as titanium oxide, chromium oxide and aluminum oxide, respectively on titanium, chromium and aluminum surfaces. In some cases, it is considered desirable to enhance the plating-preventing layer by high temperature oxidation. With other materials, specific processing may be necessary to create a plating-preventing layer. The metal on which the plating-preventing layer forms may be disposed on top of the metal on which plating takes place or vice versa. To perform the electroplating, the body is connected to the plating electrode, power turned on and then the body is immersed in the plating bath.
Where isolated conductors are desired the portions of the plating-preventing layer and the metal on which it forms which are not covered by the electroplated metal are removed after the electroplating by chemically selective etching as are any underlying metal layers.
While the technique disclosed and claimed in U.S. Pat. No. 4,988,412 is a great advance in the metallization art for the microelectronics industry, more convenient means of controlling the pattern of electroplating are desirable. In particular, it would be desirable to have a non-photoresist means of controlling the pattern of electroplating and it would also be desirable to avoid the necessity of providing multiple metallization layers in preparation for the electroplating.